The present invention relates to a method and apparatus for the repair of integrated circuits. In particular, the present invention relates to spare cell architecture and the placement and the connection thereof in integrated logic circuits.
Although a variety of tools and techniques are available to check and verify a new integrated circuit (IC) design before it is submitted to the manufacturing line for production, there are design errors that cannot be detected until the design has been fully implemented, fabricated and tested at wafer and/or module level. In memory and logic circuits, redundancy can be built into the design so that spare cells are available for repair purposes. Once a design defect has been identified, it has to be isolated and replaced, or connected in a different manner or way. The isolation is typically performed by a focused ion beam (FIB), which cuts off connections to the defective cell by ion sputtering. With the addition of reactive gases and adjustments to operating parameters, ion-induced deposition of conductive material can be performed as well. This provides chip designers with the ability to evaluate the result of a fix before committing to a design change by metal layer change that is cost effective, as the designers could use a FIB machine to validate the fix before generating a new metal layer.
Replacement comes in the form of spare cells that are typically scattered around the IC. A traditional way to repair such design defects in logic circuits is to scatter redundant logic gates, such as AND gates and OR gates, around the circuit to be used as replacements. This method is acceptable so long as the defective circuit elements being replaced are also simple AND or OR gates. Complications arise when a replacement cell is needed for a more complicated logic function. For instance, to replace an XOR function, one would need to connect together two AND gates and one OR gate. However, since the simple logic gates are typically individually scattered around the circuit, the wiring that is required to string them together can get quite convoluted. Furthermore, as more and more components are being packed into smaller and smaller chip spaces, it is becoming more difficult to find routing paths to wire the simple replacement gates together to form a more advanced gate and to redirect the inputs and outputs of the defective logic. An alternative would be to scatter a complete library of logic functions throughout the circuit. However, this is not a cost effective solution because only a few of the functions in the library will be used and a lot of them will sit idle.
A more versatile solution calls for the use of configurable logic blocks. For instant, U.S. Pat. No. 6,255,845 to Wong et al. teaches the combination of one or more inverters with a configurable logic building block, like a multiplexer, to form a spare cell that can be configured to perform a plurality of different logic-gate functions. Initially, the inputs and outputs of the inverters and the configurable logic block are not connected together in any particular manner. In their spare state, the inputs of all circuits within the spare cell are tied to a reference voltage, e.g. Vcc or Vss, available on the IC. To use the spare cell, one or more input connections to the reference voltage are cut, and the inputs and outputs are selectively interconnected to each other and/or to signals and elements of the pre-defined logic circuit on the chip. The teachings of Wong et al. help reduce the number of spare cells needed, as well as the number of connection needed to form advanced gates. However, in some cases, routing paths may need to be found to bridge the inverters to the reconfigurable logic block, and, if necessary, from the reconfigurable logic block to a flip-flop. Since the dense circuitry used in most IC chips causes it to be difficult to find routing paths and since making electrical connections with FIB is a slow process, one objective of the present invention is to provide a spare cell structure that does not require as many internal connections to activate. The spare cell logic described in the Wong et al. patent does not take into account the path routings for any logic equation that can be implemented by the spare cells.
Another critical problem confronting IC layout designers is the need to have a balanced clock tree in order to maintain synchronous logic. However, the need to connect clock pins of the flip-flops through routing paths of unpredictable distances to the existing clock trees can easily disrupt a delicately balanced clock tree. Therefore,. it is another objective of the present invention to provide a spare cell structure that does not upset a predefined balanced clock tree.
The above objectives have been achieved by spare cells in the form of configurable combinatorial networks (CCN) that are placed strategically throughout a custom IC as spare cells. The spare cells can be configured to perform a variety of Sum of Product (e.g. XOR, NOR, or more complex logical functions) logic functions, without the need for additional inverters, by connecting either a power supply or ground to specific locations using metal layer modification. There are two input buses feeding into a CCN: a functional input bus and an equation input bus; each of these buses having different functions. The output of the CCN can be connected to a D flip-flop (DFF) having its clock pin connected to a predefined clock tree. The functional input bus carries data for the CCN, while the equation input bus carries the configuration control signals that specify the function of the CCN.
To facilitate efficient FIB repairs, the spare cell CCN, and DFFs are placed (during the integrated circuit""s design phase) near a logic area where a need for defective cell replacement is determined to be highly probable. Connection paths between a spare cell and the nearby logic area are defined in such a way that automatic placement routing is guaranteed to be present near the desired logic area, so that the activation of the CCN would not upset the delicately balanced clock tree.